Job Title: FPGA RTL Design Engineer – 5G Wireless Domain

Location: Anywhere in Canada

Experience: 10+ years

About the Role:

FPGA RTL Design Engineers with deep expertise in the wireless communication domain, who can develop algorithms with the aid of MATLAB-based simulations and translate them into efficient RTL implementations. You will work closely with the customer to develop cutting-edge wireless signal processing blocks and ensure optimal mapping from algorithm to RTL while maintaining performance, area, and power efficiency.

Key Responsibilities:

Work with system architect to understand wireless PHY layer algorithm requirements and develop/model in MATLAB/Simulink.
Translate MATLAB models to RTL for hardware realization
Develop RTL architecture and microarchitecture based on algorithm requirements
Implement RTL ( VHDL ) for wireless signal processing blocks (e.g., FFT/IFFT, filters, channel estimation, MIMO detection, etc.).
Perform functional verification, linting, and synthesis of RTL designs
Implement on FPGA systems and validate the performance
Collaborate with verification, and firmware teams to ensure end-to-end integration and functionality
Optimize designs for power, performance, and area (PPA) targets
Support bring-up and on-board validation as required

Required Skills & Experience:

Skilled in architecting complex FPGA designs for high throughput
Strong RTL design skills targeting FPGA in VHDL mandatory
Good knowledge of digital signal processing fundamentals
Proficient in MATLAB/Simulink for algorithm modeling, fixed-point conversion, and simulation
Solid understanding of wireless communication standards (e.g., 5G ORAN, NR, LTE, Wi-Fi, etc.)
Experience in implementing wireless PHY layer blocks in RTL
Exposure in Altera Agilex devices and AMD Zynq RFSoC devices preferred
Experience in upper layer protocol implementation in wireless domain
Familiarity with verification methodologies (UVM/SystemVerilog preferred)
Experience in FPGA design flow including synthesis, implementation, STA and timing closure
Good debugging skills and ability to analyze RTL and simulation mismatches

Preferred Qualifications:

M.Tech / B.Tech in Electronics, Electrical, or a related field
Experience with FPGA tools (e.g., Xilinx, Intel/Altera)
Knowledge of scripting languages like Python, Tcl, or Perl
Familiarity with tools such as ModelSim, Questa, Synopsys DC, VCS, SpyGlass, or Vivado

Extend Information Systems Inc.

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