About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

This is an existing vacancy.

Your Team, Your Impact

The DFT Manager is responsible for leading the definition, implementation, and execution of Design for Test (DFT) strategies across complex silicon designs. This role ensures high test coverage, manufacturability, and product quality while balancing cost, schedule, and performance constraints. The DFT Manager leads a team of DFT engineers and works cross‑functionally with design, verification, manufacturing, product engineering, and external partners.

What You Can Expect

Own and define the overall DFT architecture and methodology for SoCs, ASICs, or IP blocks across multiple programs.
Develop and maintain DFT best practices, automation flows, and documentation.
Lead the planning, insertion, and validation of DFT features such as:
- Scan (full scan, compression, EDT)
- ATPG and fault modeling (stuck‑at, transition, cell‑aware, path delay)
- BIST (logic BIST, memory BIST)
- Boundary scan (IEEE 1149.x), IJTAG, and DFT for IOs and analog blocks
Ensure high test coverage while minimizing area, power, and timing impact.
Drive testability requirements from early architecture through tape‑out.
Review and sign off on DFT readiness at key milestones (RTL freeze, netlist, tape‑out).
Collaborate with:
- Design and physical teams to resolve DFT timing, congestion, and implementation issues
- Product engineering and manufacturing to support silicon bring‑up, yield learning, and volume production
- ATE and test program teams for test pattern delivery and deployment
Manage and mentor a team of DFT engineers, including:
- Technical direction and design reviews
- Performance management and career development
Interface with EDA vendors on tool usage, flows, and feature requirements.

What We're Looking For

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
8+ years of hands‑on DFT experience with increasing technical or leadership responsibility
Strong expertise in:
- Scan architecture and ATPG methodologies
- Memory and logic BIST
- Fault coverage analysis and debug
- DFT insertion and verification flows
Solid understanding of:
- Digital design and verification
- Timing, power, and physical design interactions
- Silicon manufacturing and test processes
Proficiency with Tessent EDA tools
Experience taking multiple designs from concept through successful production.

Preferred Qualifications

Previous people management or technical leadership experience
Strong scripting skills (e.g., Tcl, Python) for automation
Experience with advanced nodes and low‑power designs
Exposure to heterogeneous designs (multi‑die, chiplets, or mixed‑signal SoCs)
Excellent communication skills and ability to influence cross‑functional teams

Expected Base Pay Range (CAD)

142,100 - 189,400, $ per annum

Additional Compensation And Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

Marvell Technology

Open Positions

DFT Manager